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How DDR SDRAM and clock signal work together

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#1 Tooqules


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Posted 06 January 2017 - 01:11 PM

Hey! So I've been tinkering with hardware and software a bit over the last few (ok, maybe 10...) years and I'm finally biting the bullet and going for my comptia A+ cert. I'm reading up about the evolution of RAM and get to the part where my text (Mike Meyers) talks about "doubling the throughput...by making two processes for every clock cycle" (p. 155). I've done some googling, but I still can't figure out how one wire, with one square wave can send multiple signals in one cycle (I'm guessing that the answer is "it can't" but I'd appreciate understanding where my mental leap made a wrong turn).

Also, during my online search, I was reading more about the clock signal and how it uses a grid (tree) to keep the electronics in time. The things I've read state how important timing is, but wouldn't there be the tiniest of differences in reception of signal depending on where the component sat in the tree? And shouldn't that mess everything up?

Thank you for any insight you can offer!

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#2 shadow_647


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Posted 08 January 2017 - 08:31 AM

Difference from SDR vs DDR1 is that you have 5 main states on the bus.


High voltage, low voltage, the transition from high to low or low to high and off.


best i can tell the different from SDR to DDR1 in regards to the I/O bus would be if SDR only considered the high voltage as data and not low voltage states, were as DDR1 bus uses both high and low as data.


SDR 133mgz and ddr1 266mgz are both 133mgz ram speed as you know but for marketing reasons the powers that be started to claim the ram was 266mgz even though that's just the I/O bus that's able to send 2x date in any given clock signal at a higher latency to read whats going on but that's only the I/O bus and has nothing to do with the ram.

computer system bus as far as a i know are all 64bit wide.


As well on a oscilloscope the I/O bus is a sine wave and not a square wave form.


Were as DDR1 the low voltage state and the high voltage state are both used for data, this would 2x the bus at the same clock speed vs the older SDR


Other thing thats funny is memory timings and I/O bus speed seem to conceal each other out, the more bus speed you have the higher the latency for the memory to do anything,i would guess theirs buffer ram at both ends of the bus as well.


its all most a oxy moron topic in a lot of ways but good for marketing reasons, worse iv seen so far on this topic was some video card being sold that tried to claim the ram was 7000mgz, true speed of the ram was probably 300~400mgz with really lame timings, every time i see that topic as well it gets on my bad side cus i know its only done for marketing reasons, most aren't very smart when it comes to computers they see 700mgz vs 7000mgz and guess what they go for, biger numbers mean better right even if it changes nothing.


As well iv all ways looked at this topic like i did for HDDs when they changed from S-ata from P-ata with the same drive one that can only send or receive data at say 40megs sec even if your I/O bus can do 120megs sec the drive can only do 40 so your caped at 40, putting the same drive on a I/O bus that can do say 4000Megs sec changes little to nothing, your still caped at 40Megs sec seeing as that's all the drive can do so my self iv never understood why they pumped memory I/O buses.


When it comes to memory though benchmarks pumping the I/O teh way they did, did show a difference, that should only happen if the ram was faster at read/wright then the I/O bus like the Example of the HDD if the bus was 20Megs sec but the drive was 40Megs sec then of course if you pumped up the awesome on the I/O bus for the hdd you raise the bar on data transfer speed.


Other thing too about some types of memory benchmarks i wonder how they work seeing as theoretical maximum memory bandwidth is referred to as the "burst rate," which may not be sustainable.


Only sustainable memory speed should be the only thing ever considered for anything in regards to how fast you can read/write from memory.


I've done some googling, but I still can't figure out how one wire, with one square wave can send multiple signals in one cycle (I'm guessing that the answer is "it can't" but I'd appreciate understanding where my mental leap made a wrong turn).



I kind of see what you mean though by this if a cycle is from high~low or low~high voltage all you can send is one bit of data, on the other hand if you read both high and low and consider both as data then you would get two bits.

If we were talking about a strobe light a full cycle might be off/on/off, you can get two bits of data off that.


Part that gets me way confused in my research was quad bus pumping, supposedly they have twin electrical signwaves going at the same time, if we were talking about a strobe light and not electricity i don't see how you could do that with out doing more flashes per min, its on or its off its high or its low its 1 or its 0 or you have more per min/mhz.




Btw TY for you post, i use to do hardware reserch all the time and i love this kind of topic.

Edited by shadow_647, 08 January 2017 - 08:32 AM.

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