Jump to content


Register a free account to unlock additional features at BleepingComputer.com
Welcome to BleepingComputer, a free community where people like yourself come together to discuss and learn how to use their computers. Using the site is easy and fun. As a guest, you can browse and view the various discussions in the forums, but can not create a new topic or reply to an existing one unless you are logged in. Other benefits of registering an account are subscribing to topics and forums, creating a blog, and having no ads shown anywhere on the site.

Click here to Register a free account now! or read our Welcome Guide to learn how to use this site.


If PCI-e uses a point to point serial connection, what's the point of 16 lanes?

  • Please log in to reply
1 reply to this topic

#1 Spellbinder2050


  • Members
  • 3 posts
  • Local time:03:38 PM

Posted 06 August 2015 - 05:07 AM

To the IT guys out there,

I read in the Comp TIA book that PCI-e uses a point to point serial connection, as opposed to PCI's parallel communication, to connect a PCI-e device to the PCI-e bus and thus the external data bus. This basically means that bits are transferred using a pair of wires (a lane) as opposed to traveling across 32 wires (parallel communication).

The book says that bits have to get from device to device at the same time or else they need "high speed checking of the data," so it's difficult to make parallel communication bits move faster and get faster results. This is not a problem with serial communication, which gives it the ability to shoot bits back and forth a lot faster.

However, if PCI-e can use up to 16 lanes, wouldn't that imply that it's using some kind of parallel communication? The book doesn't go into detail about this.

BC AdBot (Login to Remove)


#2 Platypus


  • Global Moderator
  • 15,786 posts
  • Gender:Male
  • Location:Australia
  • Local time:07:38 AM

Posted 06 August 2015 - 07:20 AM

Data is physically transmitted as bits, but this always relates to them as the components of bytes and multiples of bytes (e.g. words, doublewords, being 2 bytes and 4 bytes grouped respectively). Parallel multiplies speed by increasing clock rate or data width. So your mention of 32 data paths on a parallel bus passes 4 bytes each clock, and those bytes all relate to one another by address. The practical speed is limited as you say by the requirement for the data on each line (wire) to arrive within a very tightly controlled time frame to avoid data errors. Any error affects the entire data content of the bus at the time it occurs and requires a re-send.


Serial data transmission is self clocking, and since it arrives "when it arrives", tiny variation in timing is not going to produce a data error such as could occur with parallel.


Since a data block sent on a parallel bus occupies the entire bus, operations that would like to send data concurrently have to do it by time slicing. With a multi-lane serial bus, the lanes can operate in a parallel style, with related data travelling on several lanes and being reassembled at the destination. But equally, concurrent operations could send different data down each lane simultaneously, without any parallelling of the content.

Top 5 things that never get done:


0 user(s) are reading this topic

0 members, 0 guests, 0 anonymous users