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Posted 25 March 2010 - 04:12 PM
Posted 25 March 2010 - 09:00 PM
Edited by ReviverSoft, 25 March 2010 - 09:01 PM.
Posted 25 March 2010 - 09:18 PM
Posted 26 March 2010 - 08:58 PM
^ Hope that explains what QPI & DMI mean.
A CPU interconnect is a data path that has the bandwidth AND latency to handle CPU-to-CPU communication. In the case of Nehalem & Westmere, the CPU interconnect is QPI. Of course, this is only apparent when you see a multi-processor diagram:
In that diagram, each of the CPUs has two QPI channels, one going to the other CPU, and one going to the IOH. The QPI channel is a CPU interconnect, as it connects two CPUs. It is also capable of performing very well as an I/O interconnect, and that's its primary use in the Bloomfield, Lynnfield and Clarksfield CPUs. In the Arrandale & Clarkdale, the QPI connects the CPU to the memory controller, where the bandwidth and latency demands placed on it are similar to those of a CPU interconnect.
For DMI, the story is VERY different. EVERY transfer across that interface is either I/O traffic, or I/O management traffic. This is an I/O interconnect, and ONLY an I/O interconnect.
Edited by ReviverSoft, 26 March 2010 - 09:03 PM.
Posted 27 March 2010 - 11:46 AM
Posted 11 August 2010 - 09:02 AM
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