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# Can Someone Explain Architecture?

5 replies to this topic

### #1 BigE23

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Posted 23 May 2008 - 07:36 PM

What exactly is the difference between 90nm, 65nm, and 45nm and what effect does it have on performance. I'm sure it may sound like a foolish question to you veterans, but I'm just trying to learn this stuff, so your help is appreciated. Thanks.

### #2 rowal5555

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Posted 23 May 2008 - 07:51 PM

BigE23.

There is no such animal as a foolish question here at BC, LOL.

Basically, in your question, 45nm is only half the width of 90nm.
The width of the tracks on a Printed Circuit Board are measured in NanoMeters, so the skinnier you can make them then the more you can cram into the same space, hence how all our appliances are getting smaller and smaller.

A nanometer is 1,000,000,000 of a metre so it is getting pretty skinny.

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### #3 BigE23

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Posted 23 May 2008 - 09:03 PM

Thanks. I understand the physical parameters, but how does it translate to performance? If I see two processors that have exactly the same parameters, except one is 90nm, and the other is a 45nm, is there a performance gain and why? If not, what is the benefit of having chips with the same parameters, except one is 90nm vs 45nm?

### #4 rowal5555

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Posted 24 May 2008 - 12:05 AM

I'm afraid I don't know the answer to that. From a purely practical point of view I would have to say that, all other things being equal, the larger tracks would carry more data than the smaller ones - like comparing the output from a garden hose and a fire hose.

I suspect that gains in performance in parts with the smaller tracks would be more to do with improvements in the technology at the ends of the tracks rather than the size of the tracks themselves, but we will hope that someone with more knowledge will jump in.

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### #5 dc3

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Posted 24 May 2008 - 10:55 AM

One of the trade offs of the smaller traces compared to the larger ones is heat. The smaller trace will have a smaller amount of ampacity which means that it will create more heat than the larger trace doing the same amount of work. Heat is the one thing that effects and ages all electronics.

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### #6 Platypus

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Posted 24 May 2008 - 08:26 PM

A little technical distinction first up:

Architecture is the structural design of a microprocessor, GPU or whatever (the implementation of registers, buses, caches, pipelines, instruction set etc) that determines how a particular chip functions. It's not directly related to the fabrication size, 65nm, 45nm etc. However fabrication size can have an effect on the architecture that is feasible on a given die size.

In other words, as the fabrication size reduces, (track widths and transistor junction size within the chip), you can pack more processing power into the same space. You could have more cache, more pipelines, more transistors, and because this is related to area, the space increase is a power of 2. Alternatively, production costs could be reduced by getting more of the original chip design from the same amount of silicon.

However, if the same design running at the same speed is fabricated at two sizes, there would be no performance difference expected between them. You would expect the smaller fabrication size to operate a little cooler. So in other words by reducing fabrication size, from the same amount of silicon you could get more of a smaller, cheaper, cooler running version of the same chip, more of a faster clocking processor that needs no more cooling than the slower ones, or the same number of an enhanced version (eg more cache). All without changing the basic design (architecture) of the chip.

This is mostly because of capacitance. As dc3 pointed out, the smaller fabrication size will paradoxically increase the resistance of the current paths within the chip. However this will be compensated for in two ways. Because everything will move closer together, the track paths will be shorter. And the capacitance between elements (especially transistor junctions) will reduce. Because capacitance is determined by area, the reduction in capacitance is to the power 2 (squared), compared to the increase in capacitance caused by them being physically closer together, which is a 1-to-1 increase. So you get more capacitance reduction than the ratio of size reduction in nm.

Capacitance is significant, because in a digital circuit using CMOS transistors, current flows during the transition between low and high states & vice versa (0 to 1, 1 back to 0), and the vast majority of that current is being used to charge and discharge capacitance. The current increases as the frequency increases, and decreases as the capacitance decreases.

So a smaller die fabrication process will have less loss in capacitance, and will either draw less current (and hence run cooler) for the same performance, or be able to run faster for the same current consumption & hence heat output. (This assumes no change in supply voltage. If the operating voltage can be reduced as well, further reductions in power consumption are possible.)

As well as capacitive loading, there is also the reduction in physical distance the current has to travel between logic gates inside the chip. The shorter the distance, the shorter the time physically taken for data to move around inside the processor. This also raises the clock speed the device can potentially run at before timing issues begin to limit how short a time each operation can possibly take - significant at multi-gigaherz clock speeds.

Edited by Platypus, 24 May 2008 - 08:30 PM.

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